Design & Simulation Of High Gain Operational Amplifier For 12 Bit Pipelined Analog To Digital Converter Using Reduced Complexity Algorithm

--This paper describes the design and analysis of High gain and widest bandwidth operational amplifier for Analog to Digital conversion application. Different Techniques are used to enhance the output characteristics performance. These amplifiers demonstrate the highest frequency and widest bandwidth of operation for amplifier using reduced complexity algorithm. This paper presents an improved circuit technique to improve the output performance. In this algorithm we are using merely a single operational amplifier for multiplication as well as amplification which enhance the power consumption and output characteristics without any degradation. Switched Capacitor Operational amplifier technique is used to reduce more power consumption. This Proposed work presents an improved architecture with reduced circuit components and complete circuit realization of its individual circuit blocks. This work is an effort to apply circuit techniques to implement a low cost, high-resolution A/D converter that can be easily integrated with a standard CMOS technology. This Proposed architecture is analyzed at 0.35μm technology using Mentor Graphics at 3.3V power supply. Advantages and disadvantages of the architecture are also discussed. Good agreement between measured and simulated results indicates the validity of our design methodology. Keyword-power efficiency, residue voltage, operational amplifier, CMOS technology